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february 2017 docid029927 rev 2 1 / 34 this is information on a product in full pro duction. www.st.com STBC03 li - ion linear battery charger with ldo and load switches datasheet - production data features ? charges single - cell li - ion batteries with cc/cv algorithm and charge termination ? fast charge current up to 650 ma adjustable by external resistor ? pre - charge current from 1 ma ? adjustable floating voltage up to 4.45 v ? integrated low quiescent ldo regulator ? automatic power path management ? auto - recharge function ? embedded protection circuit module (pcm ) featuring battery overcharge, battery over - discharge and battery overcurrent protections ? charging timeout ? shipping mode feature allows battery low leakage when over - discharged ? very low battery leakage in over - discharge and shutdown mode ? charger enable input ? charge/fault status output ? battery voltage pin to allow external gauging ? two 3 spdt load switches ? available in flip chip 30, 400 m pitch package ? rugged 4 kv hbm, esd protection on the most critical pins applications ? smart watches and wearable devices ? fitness and medical accessories ? li - ion and other li - poly battery rechargeable equipment description the STBC03 is a highly integrated power management, embedding a linear battery charger, a 150 ma ldo, 2 spdt load switches, and a protection circuit module (pcm) to prevent the battery from being damaged under fault conditions. the STBC03 uses a cc/cv algorith m to charge the battery; the fast charge and the pre - charge current can be both independently programmed using dedicated resistors. the termination current is set to 5% of the programmed fast charge current, but has fixed values for fast charge currents lo wer than 20 ma. the battery floating voltage value is programmable and can be set to a value up to 4.45 v. the STBC03 also features a charger enable input to stop the charging process anytime. the STBC03 is automatically powered off from the connected batt ery when the in pin is not connected to a valid power source (battery mode). a battery under/overtemperature condition can be detected by using an external circuitry (ntc thermistor). the STBC03 draws less than 10 na from the connected battery in shipping mode conditions, so to maximize the battery life during shelf life of the final application. the device is available in the flip chip 30 package.
contents STBC03 2 / 34 docid029927 rev 2 contents 1 application schematic ................................ ................................ .... 6 2 pin configuration (top through view) ................................ ............. 7 3 maximum ratings ................................ ................................ ............. 9 4 electrical characteristics ................................ .............................. 10 5 typical performance characteristics ................................ ........... 14 6 functional pin description ................................ ............................ 18 6.1 gnd, agnd ................................ ................................ .................... 18 6.2 ntc ................................ ................................ ................................ . 18 6.3 iset and ipre ................................ ................................ ................ 18 6.4 batms, batms_en ................................ ................................ ...... 18 6.5 batsns, batsnsfv ................................ ................................ ..... 19 6.6 bat ................................ ................................ ................................ . 19 6.7 in ................................ ................................ ................................ .... 19 6.9 sys ................................ ................................ ................................ . 20 6.10 ldo ................................ ................................ ................................ . 20 6.11 wake - up ................................ ................................ ....................... 20 6.13 chg ................................ ................................ ................................ 21 6.14 cen ................................ ................................ ................................ 21 6.15 sd ................................ ................................ ................................ ... 22 6.16 sw1_oa, sw1_ob, sw1_i, sw2_oa, sw2_ob, sw2_i ............. 22 6.17 sw_sel1 and sw_sel2 ................................ ............................... 22 7 block diagram ................................ ................................ ................ 23 8 operation description ................................ ................................ ... 24 8.1 power - on ................................ ................................ ......................... 24 8.2 battery charger ................................ ................................ ................ 24 8.3 battery temperature monitoring ................................ ....................... 28 8.4 battery overcharge protection ................................ ......................... 28 8.5 battery over - discharge protection ................................ ................... 28 8.6 battery discharge overcurrent protection ................................ ........ 28 8.7 battery fault protection ................................ ................................ .... 28 8.8 floating voltage adjustment ................................ ............................ 29 8.9 input overcurrent protection ................................ ............................ 29
STBC03 contents docid029927 rev 2 3 / 34 8.10 sys short - circuit protection, ldo current limitation ........................ 29 8.11 in overvoltage protection ................................ ................................ 29 8.12 shutdown mode ................................ ................................ .............. 29 8.13 therm al shutdown ................................ ................................ ........... 29 8.14 reverse current protection ................................ .............................. 29 9 package information ................................ ................................ ..... 30 9.1 flip chip 30 (2.59x2.25 mm) package information .......................... 30 10 ordering information ................................ ................................ ..... 32 11 revision history ................................ ................................ ............ 33
list of tables STBC03 4 / 34 docid029927 rev 2 list of tables table 1: typical bill of material (bom) ................................ ................................ ................................ ........ 6 table 2: pin description ................................ ................................ ................................ .............................. 7 table 3: absolute maximum ratings ................................ ................................ ................................ ........... 9 table 4: thermal data ................................ ................................ ................................ ................................ . 9 table 5: electrical characteristics ................................ ................................ ................................ ............. 10 table 6: charging current setting ................................ ................................ ................................ ............. 18 table 7: sys voltage source ................................ ................................ ................................ .................... 20 table 8: chg pin state ................................ ................................ ................................ ............................. 21 table 9: sw_sel1, sw_sel2 operation ................................ ................................ ................................ . 22 table 10: i fast and i end ................................ ................................ ................................ ............................. 25 table 11: flip chip 30 (2.59x2.25 mm) package mechanical data ................................ .......................... 31 table 12: ordering information ................................ ................................ ................................ ................. 32 table 13: document revision history ................................ ................................ ................................ ........ 33
STBC03 list of figures docid029927 rev 2 5 / 34 list of figures figure 1: STBC03 application schematic ................................ ................................ ................................ .... 6 figure 2: pin configuration top through view ................................ ................................ .............................. 7 figure 3: battery mode 3 v ldo load transient response ................................ ................................ ........ 14 figure 4: thermal management ................................ ................................ ................................ ............... 14 figure 5: vin mode, overvoltage protection ................................ ................................ ............................. 14 figure 6: pre - charge to fast charge mode transition threshold ................................ ................................ 14 figure 7: pre - charge to fast c harge mode transition deglitch ................................ ................................ ... 15 figure 8: pre - charge to fast charge mode to no charge mode transition ................................ ................. 15 figure 9: wake - up pin operation ................................ ................................ ................................ .............. 15 figure 10: vin plug, charging initialization ................................ ................................ ............................... 15 figure 11: wake - up operation, vsys and ldo rise overview ................................ ................................ . 16 figure 12: wake - up operation, vsys and ldo rise detail ................................ ................................ ....... 16 figure 13: vin plug, charging initialization battery mode to vin mode transition ................................ .... 16 figure 14: shutdown mode entry ................................ ................................ ................................ .............. 16 figure 15: vbat to vsys drop and vsys to vldo drop (10 ma) ................................ .......................... 17 figure 16: vbat to vsys drop and vsys to vldo drop (100 ma) ................................ ........................ 17 figure 17: cen operation ................................ ................................ ................................ ......................... 17 figure 18: cen operation, vin plug/unplug ................................ ................................ ............................. 17 figure 19: STBC03 block diagram ................................ ................................ ................................ ............ 23 figure 20: charging flowchart ................................ ................................ ................................ ................... 26 figure 21: end - of - charge flowchart ................................ ................................ ................................ .......... 27 figure 22: cc/cv charging profile (not in scale) ................................ ................................ ...................... 27 figure 23: flip chip 30 (2.59x2.25 mm) package outline ................................ ................................ ......... 30 figure 24: flip chip 30 (2.59x2.25 mm) recommended footprint ................................ ............................. 31
application schematic STBC03 6 / 34 docid029927 rev 2 1 application schematic figure 1 : STBC03 application schematic table 1: typical bill of material (bom) symbol value description note c in 10 f (16 v) input supply voltage capacitor ceramic type c sys 1 f (10 v) system output capacitor ceramic type r iset refer to i set charge current programming resistor film type r ipre refer to i pre pre - charge current programming resistor film type c bat 4.7 f (6.3 v) battery positive terminal capacitor ceramic type r float batsnsfv floating voltage programming resistor film type r div1, div2 100 - 200 k? battery monitor resistor divider film type r chg 10 k? charging/fault pull - up resistor (1) film type c ldo 1.0 f (10 v) ldo output capacitor ceramic type notes: (1) r chg must be calculated according to the external led electrical characteristics.
STBC03 pin configuration (top through view) docid029927 rev 2 7 / 34 2 pin configuration (top through view) figure 2 : pin configuration top through view table 2: pin description bump bump name description power in e5 - f5 input supply voltage. bypass this pin to ground with a 10 f capacitor bat a5 - b5 battery positive terminal. bypass this pin to gnd with a 4.7 f ceramic capacitor sys c5 - d5 system output. bypass this pin to ground with 1 f ceramic capacitor ldo f4 ldo output. bypass this pin to ground with 1 f ceramic capacitor ntc d1 battery temperature monitor pin agnd b4 analog ground connect together with the same ground layer gnd a3 ground programming iset a4 fast charge current programming resistor ipre d4 pre - charge current programming resistor sensing batms c4 battery voltage measurement pin batsns b3 battery voltage sensing. connect as close as possible to the battery positive terminal batsnsfv a2 floating voltage sensing. connect as close as possible to the battery positive terminal digital i/os cen b1 charger enable pin. active high. 500 k internal pull - up (to ldo) chg e1 charging/fault flag. active low (open drain output) wake - up d2 shipping mode exit input pin. active high. 50 k internal pull - down sw_sel2 c1 load switch 2 selection input (refer to ldo level)
pin configuration (top through view) STBC03 8 / 34 docid029927 rev 2 bump bump name description batms_en c2 battery monitor enable input (refer to ldo level) sw_sel1 b2 load switch 1 selection input (refer to ldo level) sd a1 shutdown input signal (refer to ldo level). when low, the STBC03 exits ship mode. it cannot be left floating switch matrix sw1_i f3 load switch spdt1 input (1.8 v to 5 v range) if spdt switches are used, decoupling capacitors are recommended on input and output. capacitor values depend on a pplication conditions and requirements. if not used, connect inputs and outputs to gnd sw1_oa e4 load switch spdt1 output a sw1_ob e3 load switch spdt1 output b sw2_i e2 load switch spdt2 input (1.8 v to 5 v range) sw2_oa f2 load switch spdt2 output a (enabled/disabled by swire) sw2_ob f1 load switch spdt2 output b (enabled/disabled by swire) nc c3 - d3 not connected leave floating
STBC03 maximum ratings docid029927 rev 2 9 / 34 3 maximum ratings table 3: absolute maximum ratings symbol parameter test conditions value unit v in input supply voltage pin dc voltage - 0.3 to +10.0 v non repetitive, 60 s pulse length - 0.3 to +16.0 v v ldo ldo output pin voltage dc voltage - 0.3 to +4.0 v v sys sys pin voltage dc voltage - 0.3 to +6.5 v v sw switch pin voltage (sw1_i, sw2_i, sw1_oa, sw1_ob, sw2_oa, sw2_ob) dc voltage - 0.3 to +6.5 v v chg chg pin voltage dc voltage - 0.3 to +6.5 v v wake - up wake - up pin voltage dc voltage - 0.3 to +4.6 v v lgc voltage on logic pins (cen, sw_sel1, sw_sel2, sd,batms_en) dc voltage - 0.3 to +4.0 v v iset , v ipre voltage on iset, ipre pins dc voltage - 0.3 to +2 v v ntc voltage on ntc pin dc voltage - 0.3 to v ldo v v bat , v batsns , v batsnsfv voltage on bat, batsns and batsnsfv pins dc voltage - 0.3 to +5.5 v v batms voltage on batms pin dc voltage - 0.3 to v bat +0.3 v esd human body model (in, sys, wake - up, ldo, bat, batsns, batsnsfv) js - 001 - 2012 vs. agnd pgnd and gnd 4000 v human body model (all the others) js - 001 - 2012 2000 v t amb operating ambient temperature - 40 to +85 c t j maximum junction temperature +125 c t stg storage temperature - 65 to +150 c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. table 4: thermal data symbol parameter flip chip 30 (2.25x2.59 mm) unit r thjb (1) junction - to - pcb board thermal resistance 50 c/w notes: (1) standard fr4 pcb board.
electrical characteristics STBC03 10 / 34 docid029927 rev 2 4 electrical characteristics v in =5 v, v bat = 3.6 v, c ldo = 1 f, c bat = 4.7 f, c in = 10 f, c sys = 1 f, r iset = 1 k, sd = gnd, cen = high, r ipre = 4.7 k, t a = 25 c, sw_sel1 = sw_sel2 = gnd, batms_en = gnd, wake - up floating unless otherwise specified. table 5: electrical characteristics symbol parameter test conditions min. typ. max. unit v in operating input voltage v float set 4.2 v, i fast < 250 ma 4.55 5.4 v v float set 4.45 v, i fast < 450 ma, i sys = i ldo = 0 ma 4.75 5.4 (1) v v inovp input overvoltage protection v in rising 5.6 5.9 6.4 v v inovph input overvoltage protection hysteresis v in falling 200 mv v uvlo undervoltage lock - out v in falling 3.9 v v uvloh undervoltage lock - out hysteresis v in rising 300 mv i in in supply current charger disabled mode (cen = low), i sys = i ldo = 0 a 600 a charging, v hot < v ntc < v cold , including r iset current 1.4 ma v float battery floating voltage ibat = 1 ma, batsns and batsnsfv short to battery terminal 4.179 4.2 4.221 v i bat bat pin supply current battery - powered mode (v in < v uvlo ), i ldo = 0 a 4 8 a charge terminated 9 12 a shutdown mode (by swire) 10 50 na over - discharge mode (v bat < v odc , v in < v uvlo ) 10 50 i fast fast charge current r iset = 300 650 (1) ma r iset = 430 , constant - current mode i ldo + i sys < 150 ma 450 (1) 500 r iset = 1 k, constant - current mode 200 i pre pre - charge current r ipre = 10 k, constant - current mode 20 ma v iset i set regulated voltage 1 v v ipre i pre regulated voltage 1 v
STBC03 electrical characteristics docid029927 rev 2 11 / 34 symbol parameter test conditions min. typ. max. unit v pre pre - charge to fast charge battery voltage threshold charger active 3 v i end end - of - charge current charging in cv mode for 20 ma < i fast 5 %i fast charging in cv mode for i fast < 20 ma see table 10: "ifast and iend" v ochg battery voltage overcharge threshold v bat rising, batsnsfv short to battery terminal 4.245 4.275 4.305 v v bat rising, external resistor between batsnsfv and battery terminal v float +75 mv v odc battery voltage over - discharge threshold v in < v uvlo , i ldo = 150 ma, batsnsfv and batsns short to battery terminal 2.750 2.8 2.850 v v odcr battery voltage over - discharge release threshold v uvlo < v in < v ovp , i ldo = 150 ma, batsnsfv and batsns short to battery terminal 3.0 v v wake - up wake - up voltage threshold v bat >3 v rising, i ldo = 150 ma vbat v r on - is input to sys on - resistance 0.25 0.35 r on - bs battery to sys on - resistance 0.35 0.4 r on - batms batsns to batms on - resistance i sink = 500 a 290 550 r on - loadsw1 input to output load switch 1 resistance v sw1_i = 1.8 v to 5 v sw1_oa or sw1_ob test current = 50 ma 2.0 3.8 r on - loadsw2 input to output load switch 2 resistance v sw2_i = 1.8 v to 5 v sw2_oa or sw2_ob test current = 50 ma 2.0 3.4 v ol output low level (chg) i sink = 5 ma 0.4 v i ohz high level open drain output current (chg) v oh = 5 v 1 a v il logic low input level (cen, sw_sel1, sw_sel2, batms_en, sd) 0.4 v v ih logic high input level (cen, sw_sel1, sw_sel2, batms_en, sd) 1.6 v r up cen pull - up resistor 375 500 625 k
electrical characteristics STBC03 12 / 34 docid029927 rev 2 symbol parameter test conditions min. typ. max. unit v ldo ldo output voltage i ldo = 1 ma 2.9 3.0 3.1 v v out - load ldo static load regulation i ldo = 1 ma to 150 ma 0.002 0.003 %/ma i sc ldo short - circuit current r load = 0 ? 250 350 ma t on ldo turn - on time 0 to 95% v ldo , i out = 150 ma 210 s i batocp battery discharge overcurrent protection v in v ilimscth ; v uvlo < v in < v inovp (powered from in) 1.7 a v ilimscth sys voltage threshold for input current limitation short - circuit detection v uvlo < v in < v inovp 2 v v scsys sys short - circuit protection threshold v in < v uvlo or v in >v inovp (powered from bat) v bat - 0.8 v i ntcb ntc pin bias current v ntc = 0.25 v 45 50 55 a v hot thermal hot threshold increasing ntc temperature 0.234 0.246 0.258 v v cold thermal cold threshold decreasing ntc temperature 1.28 1.355 1.43 v t hyst hot/cold temperature thresholds hysteresis 10 k ntc, ? = 3370 3 c t sd thermal shutdown die temperature 155 c t wrn thermal warning die temperature 135 c t pw - vin minimum input voltage connection time to exit from shutdown mode v bat = 3.5 v, r ntc = 10 k 240 ms t ocd overcharge detection delay v bat > v ochg , v uvlo v inovp 60 ms t dod discharge overcurrent detection delay i bat > i batocp , v in v inovp 10 ms
STBC03 electrical characteristics docid029927 rev 2 13 / 34 symbol parameter test conditions min. typ. max. unit t pfd pre - charge to fast charge transition deglitch time rising 100 ms t fpd fast charge to pre - charge fault deglitch time 10 ms t end end - of - charge deglitch time 100 ms t pre pre - charge timeout v bat = 2 v, charging 1800 s t fast fast charge timeout 14000 18000 22000 s t crdd charger restart deglitch time after end - of - charge, v bat < 3.9 v restart enabled 1200 ms v rec charger restart threshold after end - of - charge, restart enabled 3.9 v t ntcd battery temperature transition deglitch time 100 ms t pw cen valid input pulse width 15 ms t pw - wa wake - up valid input pulse width 1200 ms notes: (1) if the internal thermal temperature of the STBC03 reaches t wrn , then the programmed i fast is halved until the internal temperature drops below t wrn - 10 c typically. a warning is signaled via the chg output.
typical performance characteristics STBC03 14 / 34 docid029927 rev 2 5 typical performance characteristics figure 3 : battery mode 3 v ldo load transient response figure 4 : thermal management v bat = 3.7 v, 10 ma to 150 ma, slope 150 ma/1 s v bat = 3.7 v, vin = 5.0 v ch2 (red) = ldo 1 v/div ch3 (green) = ldo 10 mv/div ch4 (pink) = ldo load variation ch1 (blue) = v sys ch2 (red) = ldo ch3 (green) = v bat ch4 (pink) = i bat figure 5 : vin mode, overvoltage protection figure 6 : pre - charge to fast charge mode transition threshold charging is resumed when ovp disappears ch1 (blue) = vin 800 mv/div ch2 (red) = v sys 800 mv/div ch3 (green) = v bat 800 mv/div ch4 (pink) = i bat 20 ma/div ch1 (blue) = vin 800 mv/div ch2 (red) = v sys 800 mv/div ch3 (green) = v bat 800 mv/div ch4 (pink) = i bat 20 ma/div
STBC03 typical perform ance characteristics docid029927 rev 2 15 / 34 figure 7 : pre - charge to fast charge mode transition deglitch figure 8 : pre - charge to fast charge mode to no charge mode transition ch1 (blue) = vin 800 mv/div ch2 (red) = v sys 800 mv/div ch3 (green) = v bat 800 mv/div ch4 (pink) = i bat 20 ma/div ch1 (blue) = vin 800 mv/div ch2 (red) = v sys 800 mv/div ch3 (green) = v bat 800 mv/div ch4 (pink) = i bat 20 ma/div figure 9 : wake - up pin operation figure 10 : vin plug, charging initialization shutdown mode to battery mode transition. vin floating shutdown mode to vin mode transition ch1 (blue) = wak e - up pin 800 mv/div ch2 (red) = v sys 800 mv/div ch3 (green) = v bat 800 mv/div ch1 (blue) = vin 800 mv/div ch2 (red) = v sys 800 mv/div ch3 (green) = v bat 800 mv/div ch4 (pink) = i bat 20 ma/div
typical performance characteristics STBC03 16 / 34 docid029927 rev 2 figure 11 : wake - up operation, vsys and ldo rise overview figure 12 : wake - up operation, vsys and ldo rise detail ch1 (blue) = v ldo 800 mv/div ch2 (red) = v sys 800 mv/div ch3 (green) = v bat 800 mv/div ch4 (pink) = wake - up 3 v/div ch1 (blue) = v ldo 800 mv/div ch 2 (red) = v sys 800 mv/div ch3 (green) = v bat 800 mv/div ch4 (pink) = wake - up 3 v/div figure 13 : vin plug, charging initialization battery mode to vin mode transition figure 14 : shutdown mode entry ch1 (blue) = vin 800 mv/div ch2 (red) = v sys 800 mv/div ch3 (green) = v bat 800 mv/div ch4 (pink) = i bat 20 ma/div by sd pin ch1 (blue) = sd pin, 1 v/div ch2 (red) = sys pin, 1 v/div
STBC03 typical performance characteristics docid029927 rev 2 17 / 34 figure 15 : vbat to vsys drop and vsys to vldo drop (10 ma) figure 16 : vbat to vsys drop and vsys to vldo drop (100 ma) ldo loaded by 10 ma; v odc cut - off ldo loaded by 100 ma; v odc cut - off ch1 (blue) = v ldo 400 mv/div ch2 (red) = v sys 400 mv/div ch3 (green) = v bat 400 mv/div ch4 (pink) = i ldo 10 ma/div ch1 (blue) = v ldo 400 mv/div ch2 (red) = v sys 400 mv/div ch3 (green) = v bat 400 mv/div ch4 (pink) = i ldo 20 ma/div figure 17 : cen operation figure 18 : cen operation, vin plug/unplug ch1 (blue) = cen 3 v/div ch3 (green) = v bat 800 mv/div ch4 (pink) = i bat 20 ma/div ch1 (blue) = in pin 3.0 v/div ch3 (green) = cen 2.0 v/div ch4 (pink) = i bat 30 ma/div
functional pin description STBC03 18 / 34 docid029927 rev 2 6 functional pin description 6.1 gnd, agnd the STBC03 ground pins. 6.2 ntc the battery temperature monitoring pin. connect the battery ntc thermistor to this pin. the charging cycle stops when the battery temperature is outside of the safe temperature range (0 c to 45 c). when the charging cycle is completed, the ntc pin goes to a high impedance state, therefore the ntc thermistor can be also used, together with an external circuitry, to monitor the battery temperature while it is being discharged. if the ntc thermistor is not used, a 10 k resistor must be connected to ensure prop er ic operations. 6.3 iset and ipre fast and pre - charge current programming pins. connect two resistors (r iset , r ipre ) to ground to set the fast and pre - charge current (i fast , i pre ) acco rding to the following equation (valid for i fast , i pre > 5 ma): equation 1: ? ??? = ? ???? ? ???? ? ? ; ? ???? = ? ???? ? ???? ? ? where v iset = v ipre = 1 v and k = 200. fast charge and pre - charge currents can be independently set from 1 ma to 650 ma. end - of - charge current value is typically 5% of the fast charging current value being set. for low charging current (i fast , i pre < 5 ma), the r iset and r ipre values in the following table must be used. table 6: charging current setting i fast , i pr e r iset , r ipre 5 ma 40.5 k 2 ma 110 k 1 ma 260 k both r iset and r ipre must be always used. short - circuit to ground or open circuit are not allowed options. 6.4 batms, batms_en battery voltage measurement. if batms_en is high, the batms pin is internally shorted to the batsns pin during normal conditions to monitor the battery voltage using external components (c and embedded adc). the internal path from batms pin to the battery is open ed in case any of the following conditions occur: overcurrent, battery over - discharge, shutdown mode, short - circuit on sys or ldo. to minimize overall system power consumption, this function must be disabled. batms_en pin should be pulled low.
STBC03 functional pin description docid029927 rev 2 19 / 34 6.5 batsns, bats nsfv battery voltage sense pin. the batsns pin must be connected as close as possible to the battery positive terminal to ensure the maximum accuracy on the floating voltage and on the battery voltage protection thresholds. the batsnsfv pin can be used to fix the v float value by connecting a proper external series resistor to batsnsfv. the battery floating voltage can be set up to 4.45 v according to the following equation: eq uation 2: ?????? ??? = ?????? ??? ? ( 1 + ? ????? 1 ? ? ) ? = 4 . 2 ? ( 1 + ? ????? 1 ? ? ) ? example: to set the battery floating voltage for 4.35 v, refer to the following equation. equation 3: ? ??? = 1 ? ? ? ( ?????? ??? 4 . 2 ? ? 1 ) = 1 ? ? ? ( 4 . 35 ? 4 . 2 ? ? 1 ) = 35 . 7 ? ? if the batsnsfv pin is connected to the battery positive terminal, the floating voltage is set for its 4.2 v default value. 6.6 bat external battery connection pin (positive terminal) . a 4.7 f ceramic bypass capacitor must be connected to gnd. 6.7 in 5 v input supply voltage pin. the STBC03 is powered off from this pin when a valid voltage source is detected, meaning a vol tage higher than v uvlo and lower than v inovp . a 10 f ceramic bypass capacitor must be connected to gnd.
functional pin description STBC03 20 / 34 docid029927 rev 2 6.9 sys the internal ldo input voltage and external unregulated supply pin. the maxim um current deliverable through this pin depends on the following two conditions: ldo load and battery status. however, if none of the above loads sinks current, the maximum sys current budget is 650 ma, provided that the input voltage source can deliver th at amount of current. sys voltage source can be either in or bat, depending on the operating conditions (refer to the following table). a ceramic bypass capacitor of 1 f must be connected to gnd. table 7: sys voltage source v in v bat sys status ldo status < v uvlo < v odc (1) not powered off < v uvlo > v odc v bat (2) on > < v uvlo and < v inovp x (dont care) (3) v in on > v inovp < v odc not powered off > v inovp > v odc v bat (2) on notes: (1) v odcr if the shutdown mode or the over - discharge protection has been previously activated. (2) voltage drop over internal mosfet is not included. (3) battery disconnected (0 v) or fully dischar ged. resistive short - circuit is not supported for safety reasons. 6.10 ldo ldo output voltage pin. the maximum current capability is anyhow 150 ma. a 1 f ceramic bypass capacitor must be connected to gnd. 6.11 wake - up wake - up input pin. to restore normal operations of the STBC03, so to exit from a shutdown condition, connect the wake - up pin to the battery voltage. the STBC03 is enabled to operate in normal conditions again, only if the battery voltage is higher than v odcr (3 v). a deglitch delay is implemented to prevent unwanted false operations. the above - described wake - up pin functionality is disabled when a valid vin voltage source is detected. the pin has an internal 50 k pull - down resistor.
STBC03 functional pin description docid029927 rev 2 21 / 34 6.13 chg active low, open drain charging/fault flag output pin. the chg provides status information about vin voltage level, battery charging and faults by toggling at different frequencies as reported in the table b elow. table 8: chg pin state device state chg pin state note not valid input (v in < v bat or v in > v inovp or v in < v inuvlo ) high z (high by external pull - up) in case of synchronous alarm events, the highest toggling frequency has higher priority. example : ntc warning and eoc are concurrent events. ntc warning, signaled by toggling chg at 16.2 hz is the only signal available till the battery temperature goes back to a safe range (0 c to 45 c). if an eoc condition is still present then a 4.1 hz toggling s ignal is present. valid input (v in >v inuvlo , v in < v inovp , v bat < v in and cen low) low end - of - charge (eoc) toggling 4.1 hz (until usb is disconnected) charging phase (pre and fast) toggling 6.2 hz overcharge fault toggling 8.2 hz charging timeout (pre - charge, fast charge) toggling 10.2 hz battery voltage below v pre after the fast charge starts toggling 12.8 hz charging thermal limitation (thermal warning) toggling 14.2 hz battery temperature fault (ntc warning) toggling 16.2 hz 6.14 cen internal cc/cv charger block enable pin. a low logic level on this pin disables the internal cc/cv charger block. transitioning cen from high to low and then back to high, allows the cc/cv charger block to be restarted if it was stopped due to one of the following conditions: ? charging timeout (pre - charge, fast charge) ? battery voltage below v pre after the fast charge has already started ? end - of - charge cen has no effect if the charging cycle has been stopped by a battery overcharge condition. if the cc/cv charger stops the charging cycle due to an out of range battery temperature, a low logic level on the cen pin disables the cc/cv charger and resets the charging timeout timers. if cen is set high, the cc/cv charger restarts normal operations, assuming that no fault condition is detected. cen is internally pulled up to ldo via a 500 k resistor and must be either left floating or tied to ldo when the STBC03 is powered for the fir st time. should the auto - recharge function be enabled, the cc/cv charger restarts
functional pin description STBC03 22 / 34 docid029927 rev 2 automatically charging the battery if v bat goes below 3.9 v; a deglitch time delay has been added to prevent unwanted charging cycle from restarting. 6.15 sd the shutdown pin. in battery mode (if no valid vbus voltage is present) a logic high level on this pin asserts the low power consumption mode. if sd is kept high when a pulse is applied to wake - up pin the devic e exits the shutdown condition for the duration of the wake - up pulse. in shutdown mode, the battery drain is then reduced to less than 50 na. if a valid vbus voltage is present, the sd pin status has no effect and the device is always out of the shutdown c ondition. 6.16 sw1_oa, sw1_ob, sw1_i, sw2_oa, sw2_ob, sw2_i spdt load switch pins. both of spdt load switches are controlled by the digital control pins (see section below). each spdt features a typical r ds(on) of 3 . spdt load switches can be paralleled to reduce the series resistor as well as to increase the allowable flowing current. 6.17 sw_sel1 and sw_sel2 sw_sel1 and sw_sel2 drive the spdt switches according to the following table. they should be connected to gnd if not used. table 9: sw_sel1, sw_sel2 operation inputs outputs sw_sel 1 sw_sel2 sw1_oa sw1_ob sw2_oa sw2_ob 0 0 sw1_i hi - z sw2_i hi - z 1 0 hi - z sw1_i sw2_i hi - z 0 1 sw1_i hi - z hi - z sw2_i 1 1 hi - z sw1_i hi - z sw2_i
STBC03 block diagram docid029927 rev 2 23 / 34 7 block diagram figure 19 : STBC03 block diagram
operation description STBC03 24 / 34 docid029927 rev 2 8 operation description the STBC03 is a power management ic integrating a battery charger with an embedded power path function, a 150 ma low quiescent ldo, two spdt load switches and a protection circuit module (pcm) to prevent the battery from being damaged. when powered off from a single - cell li - ion or li - poly battery, and after having performed all the safety checks, the STBC03 starts charging the battery using a constant - current and constant - v oltage algorithm. the embedded power path allows simultaneously the battery to be charged and the overall system to be supplied. by contrast, when the input voltage is above the valid range, the battery supplies the ldo as well as every load connected to sys. the STBC03 also protects the battery in case of: ? overcharge ? over - discharge ? charge overcurrent ? discharge overcurrent if a fault condition is detected when the input voltage is valid (v uvlo < v in < v inovp ), the chg pin starts toggling, signaling the fa ult. the device can also be in shutdown mode (shutdown i bat < 50 na) maximizing the battery life of the end - product during its shelf life. 8.1 power - on when the STBC03 is in shutdown mode , any load connected to ldo and to sys is not supplied. an applied valid input voltage (v uvlo < v in < vi novp ) for at least 250 ms, regardless the presence of a battery or if the battery is fully depleted, allows the loads connected to sys and ldo to be sup plied, thus enabling proper system operations. the cen pin must be left floating or tied high (ldo level) during the power - on for proper operations. the STBC03 can be also turned on when vin is outside the valid range, below the conditions that the battery has at least a remaining charge of 3 v and the wake - up input is properly triggered. the STBC03 features an uvlo circuit that prevents oscillations if the input voltage source is unstable. the cen pin must be left floating or tied to a high level (ldo) whe n the STBC03 is powered. 8.2 battery charger the STBC03 allows single - cell li - ion and li - poly battery chemistry to be charged up to a 4.45 v using a cc/cv charging algorithm. the charging cycle starts when a valid input voltage source (v uvlo < v in < v inovp ) is detected and signaled by the chg pin toggling from a high impedance state to a low logic level. if the battery is deeply discharged (the battery voltage is lower than v pre ), the stb c03 charger enters the pre - charge phase and starts charging in constant - current mode with the pre - charge current ( ipre ) set. in case the battery voltage does not reach the v pre threshold within the t pre time, the charging process is stopped and a fault is signaled.
STBC03 operation description docid029927 rev 2 25 / 34 by contrast, as soon as the battery voltage reaches the v pre threshold, the constant - current fast charge phase starts operating, and the relevant charging current increases to the i fast level. likewise, if the constant current fast charge phase is not completed within t fast , meaning that v bat < v float , the charging process is stopped and a fault is signaled (chg starts toggling at 10.2 hz as long as a valid v in is present). should the battery voltage decrease below v pre during the fast charge ph ase, the charging process is halted and a fault is signaled. the constant - current fast charge phase lasts until the battery voltage is lower than v float . after that, the charging algorithm switches to a constant - voltage (cv) mode. during the cv mode, the b attery voltage is regulated to v float and the charging current starts decreasing over time. as soon as it goes below i end , the charging process is considered to be completed (eoc, end - of - charge ) and the relevant status is signaled via a 4.1 hz toggling si gnal on the chg pin, again as long as a there is a valid input source applied (v uvlo < v in < v inovp ). both i pre and the i fast values can be programmed from 1 ma to 450 ma via an external resistor, as described in the iset pin description. for any i fast pro grammed value above 20 ma, the i end value can be set either 5% or 2.5% of the i fast level. for any i fast programmed value below 20 ma, the relevant i end value is set as per the following table: table 10: i fast and i end i fast i end 20 ma 1.7 ma 10 ma 1.1 m a 5 ma 0.65 ma 2 ma 0.4 ma 1 ma 0.2 ma the battery temperature is monitored throughout the charging cycle for safety reasons.
operation descripti on STBC03 26 / 34 docid029927 rev 2 figure 20 : charging flowchart actions: ? pre - charge starts t pre timer, starts charging in cc mode at i pre ? fast - charge cc starts t fast timer, increases charge current to i fast ? fast - charge cv activates the constant - voltage control loop ? start alarm: the chg pin starts toggling
STBC03 operation description docid029927 rev 2 27 / 34 figure 21 : end - of - c harge flowchart figure 22 : cc/cv charging profile (not in scale)
operation description STBC03 28 / 34 docid029927 rev 2 8.3 battery temperature monitoring the STBC03 integrates all the needed blocks to monitor the battery temperature through an external ntc resistor. the battery temperature monitoring is enabled only during the battery charging process, in order to save power when the system is supplied from the battery. when the battery temperature is outside the normal operating range (0 - 45 c), the charging process is halted, an alarm signal is activated (the chg pin toggles at 16.2 hz) but the charging timeout timers are not stopped. if the temperature goes back to the normal operating range, before the maximum charging time has elapsed, the charging process is resumed and the alarm signal is cleared. in case of the charging timeout expires and the temperature is still outside the normal operating range, the charging process is stopped but it can be still restar ted using the cen pin. both temperature thresholds feature a 3 c hysteresis. the battery temperature monitoring block is designed to work with an ntc thermistor having r 25 = 10 k and ? = 3370 (mitsubishi th05 - 3h103f). if an ntc thermistor is not used, 1 0 k resistor must be connected to ensure the proper ic operation. 8.4 battery overcharge protection the battery overcharge protection is a safety feature, active when a valid input volta ge is connected, preventing the battery voltage from exceeding a v ochg value. should an overcharge condition be detected, the current path from the input to the battery is opened and a fault signal is activated (the chg pin toggles at 8.2 hz). when the bat tery voltage goes below v ochg , normal operations can only be restarted by disconnecting and connecting back again the input voltage (v in ). 8.5 battery over - discharge protection the batte ry over - discharge protection is a safety feature enabled only when no valid input voltage source (v uvlo < v in < v inovp ) is detected. therefore, when the STBC03 and the system are powered off from the battery, an over - discharge of the battery itself is avoi ded. should the battery voltage level be below v odc for more than t odd (over - discharge state), the STBC03 turns off and current sunk from the battery is reduced to less than 50 na. when a valid input voltage source is detected, while the battery is in an o ver - discharge state, the STBC03 charger, sys and ldo outputs are enabled. this condition persists until the battery voltage has exceeded the over - discharge released threshold (v odcr ), otherwise any other disconnection of a valid input voltage source brings back the STBC03 to a battery over - discharge state. 8.6 battery discharge overcurrent protection when the STBC03 is powered off from the battery connected to the bat pin, a discharge over current protection circuit disables the STBC03 if the current sunk from the battery is in excess of i batocp (900 ma typical) for more than t dod . the presence of a valid input voltage source or triggering the wake - up input pin, allows normal operating conditions to be restored. 8.7 battery fault protection the STBC03 features a battery fault protection. the STBC03 charger is stopped if the battery voltage remains below 1 v for at least 16 seconds.
STBC03 operation description docid029927 rev 2 29 / 34 8.8 floating voltage adjustment the STBC03 features a floating voltage adjustment, controlled via the external resistor r float connected between battery and batsnsfv. for saf ety reasons, the battery voltage overcharge threshold level (v ochg ) is linked to any floating voltage set. 8.9 input overcurrent protection when the STBC03 is powered off from a valid in put voltage source, a current limitation circuit prevents the input current from increasing in an uncontrolled manner in case of excessive load. in fact, when v sys is lower than v ilimscth , the input current is limited so to have a reduced power dissipation . as soon as v sys increases over v ilimscth , the input current limit value is increased to i inlim . 8.10 sys short - circuit protection, ldo current limitation in battery mode condition, if a short - circuit on the sys pin happens, the STBC03 is turned off (no deglitch). this short - circuit protection occurs until the sys voltage drops below v scsys . if the ldo output is in a short - circuit condition, the maximum delivered current is limited to i sc . 8.11 in overvoltage protection should the input voltage source temporarily be v in >v inovp (for example due to a poorly regulated voltage source), then the STBC03 is powered off from the b attery, thus any load connected to sys is protected. as soon as the input voltage source goes back within a valid input range (v uvlo < v in < v inovp ), the STBC03 is then powered off again from v in . 8.12 shutdown mode asserting the sd pin high forces the STBC03 to enter in shutdown mode (low power), the current sunk from the battery is reduced to less than 50 na. both sys and ldo pins are not supplied. normal operating conditions are restored either by connecting a valid input voltage source (v uvlo STBC03 is fully protected against overheating. during the charging process, if a t wrn < t sd temperature level is detected, a warning is signaled via the chg output (toggling at 14.2 hz). in this condition, the programmed i pre and i fast are temporary halved. in case of a further temperature increase (up to t sd ) the STBC03 turns off, thus stopping the charging process. this condition is latched and normal operation can be restored only by disconnecting and reconnecting back again a valid input voltage source on the v in pin. 8.14 reverse current protection when the input voltage (v in ) is higher than v uvlo , but lower than the battery voltage v bat (v uvlo < v in < v bat ) the cu rrent path from bat to in is opened so to stop any reverse current flowing from the battery to the input voltage source. this event is signaled through the chg flag.
package information STBC03 30 / 34 docid029927 rev 2 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www .st.com . ecopack ? is an st trademark. 9.1 flip chip 30 (2.59x2.25 mm) package information figure 23 : flip chip 30 (2.59x2.25 mm) package outline
STBC03 package information docid029927 rev 2 31 / 34 table 11: flip chip 30 (2.59x2.25 mm) package mechanical data dim. mm min. typ. max. a 0.50 0.55 0.60 a1 0.17 0.20 0.23 a2 0.33 0.35 0.37 b 0.23 0.26 0.29 d 2.56 2.59 2.62 d1 2 e 2.22 2.25 2.28 e1 1.6 e 0.40 se 0.20 sd 0.20 fd 0.285 0.295 0.305 fe 0.315 0.325 0.335 ccc 0.075 the terminal a1 on the bumps side is identified by a distinguishing feature (for instance by a circular "clear area", typically 0.1 mm diameter) and/or a missing bump. the terminal a1 on the backside of the product is identified by a distinguishing feature (for instance by a circular "clear area", typically between 0.1 and 0.5 mm diameter, depending on the die size). figure 24 : flip chip 30 (2.59x2.25 mm) recommended footprint
ordering information STBC03 32 / 34 docid029927 rev 2 10 ordering information table 12: ordering information order code ldo [v] package STBC03jr 3.0 v flip chip 30 400 um pitch
STBC03 revision history docid029927 rev 2 33 / 34 11 revision history table 13: document revision history date revision changes 10 - nov - 2016 1 initial release. 14 - feb - 2017 2 datasheet promoted from preliminary to production data.
STBC03 34 / 34 docid029927 rev 2 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2017 stmicroelectronics C all rights reserved

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